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NIS5135 +5 Volt Electronic Fuse
The NIS5135 is a cost effective, resettable fuse which can greatly enhance the reliability of a hard drive or other circuit from both catastrophic and shutdown failures. It is designed to buffer the load device from excessive input voltage which can damage sensitive circuits. It also includes an overvoltage clamp circuit that limits the output voltage during transients but does not shut the unit down, thereby allowing the load circuit to continue operation. Two thermal options are available, latching and auto-retry.
Features
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3.6 AMP, 5 VOLT ELECTRONIC FUSE
* * * * * * * * * *
Integrated Power Device Power Device Thermally Protected No External Current Shunt Required 10 V Maximum Input Voltage 70 mW Typical Internal Charge Pump Internal Undervoltage Lockout Circuit Internal Overvoltage Clamp ESD Ratings: Human Body Model (HBM); 2000 V Machine Model (MM); 200 V These are Pb-Free Devices
DFN10 CASE 485C
MARKING DIAGRAM
1 35 AYWWG G Pin 1-5 6 7 8 9 10 11 (flag) Function SOURCE NC ILIMIT Enable/Fault dv/dt GND VCC
Typical Applications
* Mother Board * Hard Drives * Fan Drives
35 35H A Y WW G
= Latching Version = Auto-Retry Version = Assembly Location = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2009
September, 2009 - Rev. 3
1
Publication Order Number: NIS5135/D
NIS5135
VCC
ENABLE/ FAULT
Enable
Charge Pump
SOURCE Thermal Shutdown Current Limit ILIMIT
UVLO
Voltage Clamp
dv/dt Control
dv/dt
Figure 1. Block Diagram
GND
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NIS5135
Table 1. FUNCTIONAL PIN DESCRIPTION
Pin 1-5 7 8 Function Source ILimit Enable/Fault Description This pin is the source of the internal power FET and the output terminal of the fuse. A resistor between this pin and the source pin sets the overload and short circuit current limit levels. The enable/fault pin is a tri-state, bidirectional interface. It can be used to enable or disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring circuit that the device is in thermal shutdown. It can also be connected to another device in this family to cause a simultaneous shutdown during thermal events. The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal capacitor that allows it to ramp up over a period of 2 ms. An external capacitor can be added to this pin to increase the ramp time. If an additional time delay is not required, this pin should be left open. Negative input voltage to the device. This is used as the internal reference for the IC. Positive input voltage to the device.
9
dv/dt
10 11 (belly pad)
Ground VCC
MAXIMUM RATINGS
Rating Input Voltage, operating, steady-state (VCC to GND, Note 1) Transient (100 ms) Thermal Resistance, Junction-to-Air 0.1 in2 copper (Note 2) 0.5 in2 copper (Note 2) Thermal Resistance, Junction-to-Lead (Pin 1) Thermal Resistance, Junction-to-Case Total Power Dissipation @ TA = 25C Derate above 25C Operating Temperature Range (Note 3) Nonoperating Temperature Range Lead Temperature, Soldering (10 Sec) Symbol VIN qJA Value -0.6 to 18 -0.6 to 25 227 95 27 20 1.3 10.4 -40 to 150 -55 to 155 260 Unit V C/W
qJL qJC Pmax TJ TJ TL
C/W C/W W mW/C C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the package. 2. 1 oz copper, double-sided FR4. 3. Thermal limit is set above the maximum thermal rating. It is not recommended to operate this device at temperatures greater than the maximum ratings for extended periods of time.
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NIS5135
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 5.0 V, CL = 70 mF, dv/dt pin open, RLIMIT= 10 W, TJ = 25C
unless otherwise noted.) Characteristics POWER FET Delay Time (enabling of chip to ID = 100 mA with 1 A resistive load) ON Resistance (Note 4) TJ = 80C (Note 5) Off State Output Voltage (VCC = 10 Vdc, VGS = 0 Vdc, RL = R) Output Capacitance VDS = 5 VDC, VGS = 0 VDC, RL = R Continuous Current (TA = 25C, 0.5 in2 pad) (Note 5) (TA = 80C, minimum copper) THERMAL LATCH Shutdown Temperature (Note 5) Thermal Hysteresis (Decrease in die temperature for turn on, does not apply to latching parts) UNDER/OVERVOLTAGE PROTECTION VOUT Maximum (VCC = 10 V) Undervoltage Lockout (Turn on, Voltage Going High) UVLO Hysteresis CURRENT LIMIT Kelvin Short Circuit Current Limit (RLimit = 11 W, Note 6) Kelvin Overload Current Limit (RLimit = 11 W, Note 6) dv/dt Circuit Output Voltage Ramp Time (Enable to VOUT = 4.7 V) Maximum Capacitor Voltage ENABLE/FAULT Logic Level Low (Output Disabled) Logic Level Mid (Thermal Fault, Output Disabled) Logic Level High (Output Enabled) High State Maximum Voltage Logic Low Sink Current (Venable = 0 V) Logic High Leakage Current for External Switch (Venable = 3.3 V) Maximum Fanout for Fault Signal (Total number of chips that can be connected to this pin for simultaneous shutdown) TOTAL DEVICE Bias Current (Operational) Bias Current (Shutdown) Minimum Operating Voltage (Notes 5 and 7) 4. 5. 6. 7. IBias IBias Vmin 1.5 1.0 3.1 2.0 mA mA V Vin-low Vin-mid Vin-high Vin-max Iin-low Iin-leak Fan 0.35 0.82 1.96 3.40 0.58 1.4 2.64 4.30 -12 0.81 1.95 3.30 5.2 -20 1.0 3.0 V V V V mA mA Units tslew Vmax 0.70 1.4 2.4 VCC ms V ILIM ILIM 2.3 3.1 3.5 3.9 A A Vout-clamp VUVLO VHyst 5.95 3.2 - 6.65 3.6 0.40 7.35 4.0 - V V V TSD THyst 150 175 45 200 C C Tdly RDSon Voff Cout ID ID 54 500 68 95 50 230 3.6 1.7 82 200 ms mW mV pF A Symbol Min Typ Max Unit
Pulse test: Pulse width 300 ms, duty cycle 2%. Verified by design. Refer to explanation of short circuit and overload conditions in application note AND8140/D. Device will shut down prior to reaching this level based on actual UVLO trip point.
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NIS5135
60 50 25C POWER (W) 40 30 20 10 0 80C 50C
0.1
1
10
100 TIME (ms)
1000
10000 100000
Figure 2. Power Dissipation vs. Thermal Trip Time
+12 V
11 V CC SOURCE NIS5135 ILIMIT ENABLE
10 9 8 7 6 4 RS
3
GND ENABLE 1
dv/dt 2
LOAD
GND
Figure 3. Application Circuit with Direct Current Sensing
+12 V
11 V CC SOURCE NIS5135 ILIMIT ENABLE
10 9 8 7 6 4 RS
3
GND ENABLE 1
dv/dt 2
LOAD
GND
Figure 4. Application Circuit with Kelvin Current Sensing
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NIS5135
VCC SOURCE
VCC SOURCE RS
NIS5135 ILIMIT ENABLE ENABLE
NIS5132
ILIMIT
LOAD
dv/dt
GND ENABLE
GND
dv/dt
LOAD
Figure 5. Common Thermal Shutdown
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NIS5135
4
0.46 0.44
3.75 UVLO (V) HYST (V) -25 0 25 50 75 100 125 150
0.42 0.4 0.38 0.36 0.34
3.5
3.25
3 -50
0.32 -50
-25
0
25
50
75
100
125 150
TEMPERATURE (C)
TEMPERATURE (C)
Figure 6. UVLO Turn-On
Figure 7. UVLO Hysteresis
6.72 6.7 6.68 RAMP TIME (ms) VOLTAGE (V) 6.66 6.64 6.62 6.6 6.58 6.56 -50 -25 0 25 50 75 100 125 150
1.9 1.8 1.7 1.6 1.5 1.4 1.3 -50
-25
0
25
50
75
100
125
15
TEMPERATURE (C)
TEMPERATURE (C)
Figure 8. Output Clamping Voltage
1600
Figure 9. Output Voltage dv/dt Rate
1200 CURRENT (mA)
800
400
0 0.5
0.6
0.7
0.8
FORWARD VOLTAGE (V)
Figure 10. Input Transient Response
Figure 11. Body Diode Forward Characteristics
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NIS5135
5 -40C CURRENT (A) 0C 25C 4 50C 85C 3.5 OL 1 SC 10
4.5 CURRENT (A)
3
0
0.2
0.4
0.6
0.8
1
1.2 (in2)
1.4
1.6
1.8
2
0.1 10
100 Rlimit (W)
1000
COPPER AREA
Figure 12. Thermal Limit vs. Copper Area and Ambient Temperature
2.5 2 CURRENT (A) OL CURRENT (A) 1.5 SC 1 0.5 0 0.1 10
Figure 13. Current Limit vs. Rsense for Direct Current Sensing
OL SC 1.0
-50
0
50 TEMPERATURE (C)
100
150
1
Figure 14. Direct Current Sensing Levels vs. Temperature for 33 W Sense Resistor
3.6 3.4 3.2 CURRENT (A) 3.0 2.8 2.6 2.4 2.2 2.0 -40 -20 0 20 SC OL CURRENT (A) 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 40 60 80 100
Figure 15. Current Limit vs. Rsense for Kelvin Current Sensing
10 Rsense (W)
10
OL
SC -20 0 20 40 60 80 10
1.0 -40
TEMPERATURE (C)
TEMPERATURE (C)
Figure 16. Kelvin Current Sensing Levels vs. Temperature for 18 W Sense Resistor
Figure 17. Kelvin Current Sensing Levels vs. Temperature for 39 W Sense Resistor
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NIS5135
140
ON RESISTANCE (mW)
120
100
80
60 3.0
4.0 VCC (V)
5.0
6.0
Figure 18. On Resistance vs. VCC
APPLICATION INFORMATION
Basic Operation
This device is a self-protected, resettable, electronic fuse. It contains circuits to monitor the input voltage, output voltage, output current and die temperature. On application of the input voltage, the device will apply the input voltage to the load based on the restrictions of the controlling circuits. The dv/dt of the output voltage will be controlled by the internal dv/dt circuit. The output voltage will slew from 0 V to the rated output voltage in 2 ms, unless additional capacitance is added to the dv/dt pin. The device will remain on as long as the temperature does not exceed the 175C limit that is programmed into the chip. The current limit circuit does not shut down the part but will reduce the conductivity of the FET to maintain a constant current at the internally set current limit level. The input overvoltage clamp also does not shutdown the part, but will limit the output voltage to 6.65 V in the event that the input exceeds that level. An internal charge pump provides bias for the gate voltage of the internal n-channel power FET and also for the current limit circuit. The remainder of the control circuitry operates between the input voltage (VCC) and ground.
Current Limit
device is actively limiting the current and the gate is at an intermediate level. For a more detailed description of this circuit please refer to application note AND8140. There are two methods of biasing the current limit circuit for this device. They are shown in the two application figures. Direct current sensing connects the sense resistor between the current limit pin and the load. This method includes the bond wire resistance in the current limit circuit. This resistance has an impact on the current limit levels for a given resistor and may vary slightly depending on the impedance between the sense resistor and the source pins. The on resistance of the device will be slightly lower in this configuration since all five source pins are connected in parallel and therefore, the effective bond wire resistance is one fifth of the resistance for any given pin. The other method is Kelvin sensing. This method uses one of the source pins as the connection for the current sense resistor. This connection senses the voltage on the die and therefore any bond wire resistance and external impedance on the board have no effect on the current limit levels. In this configuration the on resistance is slightly increased relative to the direct sense method since only for of the source pins are used for power.
Overvoltage Clamp
The current limit circuit uses a SENSEFET along with a reference and amplifier to control the peak current in the device. The SENSEFET allows for a small fraction of the load current to be measured, which has the advantage of reducing the losses in the sense resistor as well as increasing the value and decreasing the power rating of the sense resistor. Sense resistors are typically in the tens of ohms range with power ratings of several milliwatts making them very inexpensive chip resistors. The current limit circuit has two limiting values, one for short circuit events which are defined as the mode of operation in which the gate is high and the FET is fully enhanced. The overload mode of operation occurs when the
The overvoltage clamp consists of an amplifier and reference. It monitors the output voltage and if the input voltage exceeds 6.65 V, the gate drive of the main FET is reduced to limit the output. This is intended to allow operation through transients while protecting the load. If an overvoltage condition exists for many seconds, the device may overheat due to the voltage drop across the FET combined with the load current. In this event, the thermal protection circuit would shut down the device.
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NIS5135
Undervoltage Lockout
The undervoltage lockout circuit uses a comparator with hysteresis to monitor the input voltage. If the input voltage drops below the specified level, the output switch will be switched to a high impedance state.
dv/dt Circuit
The dv/dt circuit brings the output voltage up under a linear, controlled rate regardless of the load impedance characteristics. An internal ramp generator creates a linear ramp, and a control circuit forces the output voltage to follow that ramp, scaled by a factor. The default ramp time is approximately 2 ms. This can be modified by adding an external capacitor at the dv/dt pin. This pin includes an internal current source of approximately 85 nA. Since the current level is very low, it is important to use a ceramic cap or other low leakage capacitor. Aluminum electrolytic capacitors are not recommended for this circuit. The ramp time from 0 to the nominal output voltage can be determined by the following equation, where t is in seconds:
t 0-5 + 30e6 @ (50 pF ) C ext) C ext + t 0-5 30e6 * 50 pF
When this pin is low, the output of the fuse will be turned off. When this pin is high the output of the fuse will be turned-on. If a thermal fault occurs, this pin will be pulled low to an intermediate level by an internal circuit. To use as a simple enable pin, an open drain or open collector device should be connected to this pin. Due to its tri-state operation, it should not be connected to any type of logic with an internal pullup device. If the chip shuts down due to the die temperature reaching its thermal limit, this pin will be pulled down to an intermediate level. This signal can be monitored by an external circuit to communicate that a thermal shutdown has occurred. If this pin is tied to another device in this family (NIS5132 or NIS5135), a thermal shutdown of one device will cause both devices to disable their outputs. Both devices will turn on once the fault is removed for the auto-retry devices. For the latching thermal device, the outputs will be enabled after the enable pin has been pulled to ground with an external switch and then allowed to go high or after the input power has been recycled. For the auto retry devices, both devices will restart as soon as the die temperature of the device in shutdown has been reduced to the lower thermal limit. The thermal options are listed in the ordering table.
Thermal Protection
Where: C is in Farads t is in Seconds Any time that the unit shuts down due to a fault, enable shut-down, or recycling of input power, the timing capacitor will be discharged and the output voltage will ramp from 0 at turn on.
Enable/Fault
The Enable/Fault Pin is a multi-function, bidirectional pin that can control the output of the chip as well as send information to other devices regarding the state of the chip.
The NIS5135 includes an internal temperature sensing circuit that senses the temperature on the die of the power FET. If the temperature reaches 175C, the device will shut down, and remove power from the load. Output power can be restored by either recycling the input power or toggling the enable pin. Power will automatically be reapplied to the load for auto-retry devices once the die temperature has been reduced by 45C. The thermal limit has been set high intentionally, to increase the trip time during high power transient events. It is not recommended to operate this device above 150C for extended periods of time.
Figure 19. Enable/Fault Signal Levels
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NIS5135
4.3 V 12 mA Startup Blanking 2.64 V En/Fault + - Enable SD
1.4 V 0.58 V SD Thermal Shutdown
- + Thermal Reset
Thermal SD
Figure 20. Enable/Fault Simplified Circuit
ORDERING INFORMATION
Device NIS5135MN1TXG NIS5135MN2TXG Features Thermal Latching Thermal Auto-Retry Package DFN10 (Pb-Free) DFN10 (Pb-Free) Shipping 3000 / Tape & Reel 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NIS5135
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P CASE 485C-01 ISSUE B
D A B L1
EDGE OF PACKAGE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.40 2.60 3.00 BSC 1.70 1.90 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03
PIN 1 REFERENCE 2X 2X
0.15 C
0.15 C
0.10 C
10X
DETAIL B
(A3) A A1
SEATING PLANE
0.08 C SIDE VIEW D2
10X
A1
DETAIL A 5
C
L
e
1
SOLDERING FOOTPRINT*
2.6016
10X
K
E2
10 10X
6
2.1746
b BOTTOM VIEW
10X
0.10 C A B 0.05 C
NOTE 3
0.5651
0.3008
10X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
The product described herein (NIS5135), may be covered by one or more of the following U.S. patents; 7,099,135 and 6,865,063. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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EEE EEE EEE
CCCC CCCC CCCC
E
DETAIL A Bottom View (Optional)
EXPOSED Cu MOLD CMPD
TOP VIEW
A3
DETAIL B Side View (Optional)
1.8508
3.3048
0.5000 PITCH
DIMENSIONS: MILLIMETERS
NIS5135/D

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